New Chip Design Merges Storage and Processing to Cut Power Use

For six decades, computer architecture has relied on a strict division of labor: memory chips store data, while separate processors handle the calculations. This model, dominated by giants like Intel and Micron, has driven progress but creates a persistent inefficiency. Data must constantly travel between these two components over limited physical connections, creating a bottleneck that slows performance and drains energy.

Purab Sutradhar, an assistant professor at Boise State University, is challenging this status quo with a project called HYDRA. Supported by a National Science Foundation grant, the initiative seeks to build computing logic directly into dynamic random-access memory. By allowing the chip to process data where it is stored, Sutradhar aims to eliminate the costly back-and-forth traffic that plagues current electronics.

Integrating Logic into Memory Banks

The core challenge is that memory chips are engineered for simplicity and low cost, not complex computation. Cramming processing hardware into these devices introduces new complications regarding interference and congestion. HYDRA addresses this by using an intelligent control system that allows computing and storage to operate side-by-side without one disrupting the other. The design strategically distributes processing units throughout the memory to create short, localized paths for data.

Unlike previous approaches that added distinct AI cores to general-purpose chips, HYDRA’s architecture is built around the physical realities of the memory itself. It utilizes lean, parallel units inside high-bandwidth memory banks and more complex units outside them. A specialized control layer hides this complexity from software developers, making the diverse hardware appear uniform and easy to program.

Efficiency Gains for Low-Power Devices

The practical stakes are significant, particularly for devices with tight power budgets like smartphones, wearables, and autonomous systems. In earlier research, Sutradhar demonstrated that a memory-centric architecture could be over 22 times more energy-efficient than a high-end graphics processing unit when running encryption tasks. He expects similar improvements with HYDRA, especially for emerging security techniques and AI workloads that process mixed data types.

As reported by GN technics/hardware (en-US), this efficiency is crucial for extending battery life in portable technology. By reducing the energy required to move data, the design could enable more sophisticated on-device intelligence without the need for external cloud processing or larger, power-hungry batteries.

Validating the Design Through Simulation

Because the internal design of commercial memory chips is proprietary and inaccessible to outside researchers, Sutradhar’s team cannot simply build a physical prototype immediately. Instead, they are using a layered simulation strategy to validate the design. This involves creating a field-programmable gate array prototype to confirm the architecture works as intended, bypassing the need to fabricate custom silicon in a foundry.

This approach allows the team to iterate quickly and test the control architecture’s ability to manage the hybrid environment. While the project is in its initiation phase, it represents a potential shift in how fundamental computing hardware is structured, moving away from the traditional processor-memory split toward a more integrated model.