New Bridge Simplifies Testing for Next-Gen Data Links

SignatureIP announced MesoLink, a new connectivity bridge designed to streamline the testing of PCIe and CXL hardware. The tool addresses a persistent challenge in chip development: reconciling the high speeds of modern system boards with the slower timing constraints of prototype chips. By acting as a flexible intermediary, it allows engineers to validate designs without building fragile, custom workarounds for clock differences.

The announcement was made at the AI Infra Summit 2026 in Santa Clara, California. In this environment, system-level verification often requires running the host system at full speed while the device under test operates at a lower, stable rate. Traditionally, this mismatch has forced teams to create bespoke bridging logic, a process that is time-consuming and prone to errors. MesoLink is built to absorb this timing difference automatically, simplifying the integration process for verification teams.

Bridging the Speed Gap Between Chips

The core function of MesoLink is to translate signals between two different timing domains. On one side, it connects to the host system at its native speed and lane width. On the other side, it interfaces with the device under test at whatever generation and lane width that specific chip supports. This allows the device to communicate with the system without losing data continuity, even at very low clock rates as low as 1 MHz.

This flexibility is critical because it removes the need to redesign test infrastructure for every new chip. Engineers can bring up, debug, and validate devices across a wide range of operating speeds using the same setup. According to SignatureIP, this approach eliminates the trade-off between matching a fixed system speed or building custom logic, allowing each device to run at its optimal speed.

Beyond Prototyping to Custom Silicon

While the tool is particularly useful for FPGA-based prototyping and emulation, its applications extend further. The timing-agnostic architecture means it is also valuable for custom silicon designs. Design teams can use MesoLink to tape out their own silicon at the best possible timing, rather than constraining their design to match a fixed system requirement. This provides greater freedom in the final manufacturing process.

The IP core is available as synthesizable RTL and is also offered as an integrated package for Siemens proFPGA CS platforms. This availability allows for immediate integration into existing workflows. The tool supports PCIe Gen1 through Gen6, covering a broad range of valid lane widths from x1 to x16. This wide compatibility ensures that it can handle the diverse array of devices currently in the market.

Ecosystem Partnerships and Live Demos

SignatureIP is showcasing a live demonstration of its complete solution, including MesoLink, in collaboration with ecosystem partners Siemens HAV and Teledyne LeCroy. The demo illustrates a PCIe/CXL device running at its native generation and lane width while seamlessly connected to a system running at full speed. This real-world application highlights how the bridge maintains data integrity during high-speed transfers.

Reporting from GN auto tech/hardware notes that this development is part of a broader trend in silicon infrastructure. As AI infrastructure demands faster and more reliable data links, the ability to verify these components efficiently becomes a significant competitive advantage. By removing the friction of timing mismatches, tools like MesoLink help accelerate the development cycle for next-generation computing hardware.